1. Field of the Invention
The present invention relates to an information processing device for performing information exchange by a PCI Express bus and a non-PCI Express bus interface.
2. Description of the Related Art
In recent years, an I/O serial interface called PCI Express has been used in personal computers (PCs) and associated peripherals.
PCI Express (hereinafter abbreviated as “PCIe”) realizes a 2-Gbps transfer speed by using 1 lane and realizes a 64-Gbps transfer speed by using 32 lanes.
In PCIe, there are prescribed layer structures resulting from the three layers of a physical layer, a data link layer and a transaction layer (see FIG. 2) and the two layers of a software layer and a configuration/OS layer. PCIe is capable of changing, with software, the address map of a device that has a configuration register and is connected to a PCIe standard bus (hereinafter called a “PCIe bus”). The configuration/OS layer realizes PCI plug and play, and when a device is connected to a bus, settings and software installation necessary in order for the PC to automatically cause the device to operate are performed without the support of the user.
Because of these mechanisms, even when an address to which a device is connected differs, the same driver software can be used by using one driver per device. Conventionally, in a device connected to a bus (a non-PCIe bus), it has been necessary to perform driver development separately per hardware component when an address differs even with the same device. In PCIe, there is no longer the need to perform that driver development. That is, by using a device connected to a PCIe bus, device driver software does not have to be separately developed.
There is the desire to want to use conventional bus (non-PCIe bus)-connected devices of which creation and verification have been completed and which also have a performance record.
For that reason, there are technologies that use a device connected to a conventional bus as a device connected to a PCIe bus. For example, there are technologies that use a device connected to a PCI bus as a device connected to a PCIe bus (e.g., see Japanese Patent Application Laid-Open (JP-A) No. 2009-10920 and JP-A No. 2009-70249).
A device connected to another bus such as an AHB standard bus widely used for integration purposes has an address map that is fixed to its hardware and is incapable of being changed by software. For that reason, there are technologies that use an address conversion circuit (see FIG. 15) disposed in a PCIe configuration space to convert between a PCIe standard bus address (hereinafter called a “PCIe address”) and a non-PCIe standard bus address.
FIG. 15 is a configuration diagram showing the general configuration of one example of an address converter 118 equipped with a PCIe-AHB address conversion circuit 134 that performs conversion between a PCIe address and an AHB standard bus address (hereinafter called an “AHB address”).
In a base address register (hereinafter abbreviated as “BAR”) 132 disposed in the configuration space, a PCIe beginning address, a PCIe address width and an AHB offset address that correspond to a device connected to an AHB bus are stored beforehand.
The PCIe-AHB address conversion circuit 134 converts between a PCI address and an AHB address on the basis of information stored in the BAR 132. As one example, a case where the PCIe-AHB address conversion circuit 134 converts a PCIe address into an AHB address will be described. When an inputted PCIe address satisfies expression (1) and expression (2), the PCIe-AHB address conversion circuit 134 converts the inputted PCIe address into an AHB address by calculating an AHB address by expression (3).PCIe address≧PCIe beginning address  (1)PCIe address≦(PCIe beginning address+PCIe address width)  (2)AHB address=PCIe address−PCIe beginning address+AHB offset address  (3)
In FIG. 15, there are cases where an information processing device 10 using the PCIe-AHB address conversion circuit 134 has to perform setting depending on the device.
For example, in a case where PCIe is used, initialization of a device connected to a PCIe bus is implemented before a CPU controlling PCIe operates. Usually, initialization of the device is performed as a result of the CPU resetting the device when power is switched ON. However, there are cases where initialization of the device cannot be performed by resetting the device. For example, in a case where the device is a network-use device, the device has a unique media access control (MAC) address and is identified by this MAC address. Consequently, it is necessary to set the MAC address in the device before the CPU operates.
Further, for example, in a case where the device is a field programmable gate array (FPGA), the PCIe address width and the AHB offset address that the device uses are dependent on the circuit of that device. Consequently, it is necessary to perform setting to change the PCIe address width and the AHB offset address stored in the BAR 132 to values corresponding to that device.